1. Field of the Invention
This application generally relates to data processing systems and, more particularly, to systems in which multiple processing devices may access the same shared data stored in memory.
2. Description of the Related Art
In a multiprocessor system, or any type of system that allows more than one device to request and update blocks of shared data concurrently, it is important that some mechanism exists to keep the data coherent (i.e., to ensure that each copy of data accessed by any device is the most current copy). In many such systems, a processor has one or more caches to provide fast access to data (including instructions) stored in relatively slow (by comparison to the cache) external main memory. In an effort to maintain coherency, other devices on the system (e.g.; a graphics processing unit-GPU) may include some type of coherency (or “snoop”) logic to determine if a copy of data from a desired memory location is held in the processor cache by sending commands (snoop requests) to the processor cache directory.
This snoop logic is used to determine if desired data is contained in the processor cache and if it is the most recent copy. If so, in order to work with the latest copy of the data, the device may request ownership of the modified data stored in a processor cache line. In a conventional coherent system, other devices requesting data do not know ahead of time whether the data is in a processor cache. As a result, these devices must snoop every memory location that it wishes to access to make sure that proper data coherency is maintained. In other words, the requesting device must literally interrogate the processor cache for every memory location that it wishes to access, which can be very expensive both in terms of command latency and microprocessor bus bandwidth.
Accordingly, what is needed is an efficient method and system which would reduce the amount of latency associated with interfacing with (snooping on) a processor cache.